Webb14 apr. 2024 · In this post we are going to describe a possible method to extend one the main RISC-V ISA simulator (spike) to implement a single instruction inspired by a future extension: vector all-rounds NIST cryptography, a.k.a Zvknf (currently in draft mode).The selected instruction is the vector AES-128 all-rounds encryption. WebbAbout. For more information: www.chanjinweilouis.com. Louis is a firm believer in exceeding expectations and delivering results consistently. He has a strong passion for corporate sustainability and sustainable finance. He enjoys aligning his professional interest in sustainability with his personality of challenging himself and embedding ...
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